The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

Nov. 17, 2018
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Shasha Liu, Wuhan, CN;

Li Hong Xiao, Wuhan, CN;

EnBo Wang, Wuhan, CN;

Feng Lu, Wuhan, CN;

Qianbin Xu, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 27/06 (2006.01); H01L 27/10 (2006.01); H01L 27/11565 (2017.01); G11C 16/04 (2006.01); H01L 27/11551 (2017.01); H01L 23/31 (2006.01); H01L 21/822 (2006.01); H01L 27/11578 (2017.01);
U.S. Cl.
CPC ...
H01L 27/0688 (2013.01); G11C 16/0483 (2013.01); H01L 21/8221 (2013.01); H01L 23/3114 (2013.01); H01L 27/101 (2013.01); H01L 27/11551 (2013.01); H01L 27/11565 (2013.01); H01L 27/11578 (2013.01);
Abstract

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending vertically through the memory stack, and a semiconductor layer above the memory stack. The channel structure includes a channel plug in a lower portion of the channel structure, a memory film along a sidewall of the channel structure, and a semiconductor channel over the memory film and in contact with the channel plug. The semiconductor layer includes a semiconductor plug above and in contact with the semiconductor channel.


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