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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10678990 B1

PDFFull Text
Date of Patent:
Jun. 09, 2020

Filed:

Nov. 30, 2018

Techniques based on electromigration characteristics of cell interconnect

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Kuo-Nan Yang, Hsinchu, TW;

Chung-Hsing Wang, Baoshan Township, TW;

Yi-Kan Cheng, Taipei, TW;

Kumar Lalgudi, Fremont, CA (US);

Assignee:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Attorney:

Eschweiler & Potashnik, LLC

Primary Examiner:

Leigh M Garbowski

Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 30/394 (2020.01); H01L 23/528 (2006.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/347 (2020.01); G06F 30/373 (2020.01); H01L 27/02 (2006.01); G06F 30/396 (2020.01); G06F 119/10 (2020.01); G06F 117/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/347 (2020.01); G06F 30/373 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); H01L 23/528 (2013.01); H01L 27/0207 (2013.01); G06F 30/396 (2020.01); G06F 2117/12 (2020.01); G06F 2119/10 (2020.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01);
Abstract

In some embodiments, an initial circuit arrangement is provided. The initial circuit arrangement includes cells that include default-rule lines and non-default-rule lines. Line widths of the default-rule lines are selectively increased for a first cell in the initial circuit arrangement, thereby providing a first modified circuit arrangement. A first maximum capacitance value is calculated for the first cell of the first modified circuit arrangement. A second modified circuit arrangement is provided by selectively increasing line widths of the non-default-rule lines in the first modified circuit arrangement. A second maximum capacitance value is calculated for the first cell of the second modified circuit arrangement. A line width of a first non-default-rule line is selectively reduced based on whether the first maximum capacitance value adheres to a predetermined relationship with the second maximum capacitance value. The second modified circuit arrangement is manufactured on a semiconductor substrate.

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