The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2020
Filed:
Aug. 26, 2018
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Chun Hsiung Tsai, Hsinchu County, TW;
Chien-Tai Chan, Hsinchu, TW;
Ziwei Fang, Hsinchu, TW;
Kei-Wei Chen, Tainan, TW;
Huai-Tei Yang, Hsinchu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/223 (2006.01); H01L 21/265 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/2236 (2013.01); H01L 21/26513 (2013.01); H01L 29/665 (2013.01); H01L 29/66492 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7834 (2013.01); H01L 21/26506 (2013.01); H01L 21/28518 (2013.01); H01L 21/76897 (2013.01);
Abstract
A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cmwithin a depth range of about 0-5 nm from a surface of the strained layer.