The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2020
Filed:
Sep. 10, 2018
Applicant:
Ememory Technology Inc., Hsinchu, TW;
Inventors:
Assignee:
eMemory Technology Inc., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/06 (2006.01); G11C 17/16 (2006.01); G06F 7/58 (2006.01); H04L 9/32 (2006.01); G06F 21/86 (2013.01); H04L 9/08 (2006.01); G09C 1/00 (2006.01); H03K 3/84 (2006.01); G11C 17/18 (2006.01); H01L 27/112 (2006.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
G06F 7/588 (2013.01); G06F 21/86 (2013.01); G09C 1/00 (2013.01); G11C 7/062 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); H01L 27/11206 (2013.01); H03K 3/84 (2013.01); H04L 9/0866 (2013.01); H04L 9/0869 (2013.01); H04L 9/3278 (2013.01); H03K 19/21 (2013.01); H04L 2209/12 (2013.01);
Abstract
A method of programming a nonvolatile memory cell is provided according to an embodiment of the invention. The nonvolatile memory cell includes a substrate; and a select transistor, a following gate transistor, and an anti-fuse transistor comprising a first gate oxide layer, disposed on the substrate and coupled in series with each other. The programming method includes applying to said nonvolatile memory cell a variable DC voltage source comprising at least one high voltage part for forming a trapping path within the first gate oxide layer and at least one low voltage part for crystallizing the trapping path into a silicon filament.