The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Feb. 04, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Li-Sheng Weng, Tempe, AZ (US);

Chi-Te Chen, Folsom, CA (US);

Wei-Lun Jen, Chandler, AZ (US);

Olivia Chen, Folsom, CA (US);

Yun Ling, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/498 (2006.01); H05K 3/34 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H05K 3/28 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4853 (2013.01); H01L 23/49805 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H05K 1/112 (2013.01); H05K 1/181 (2013.01); H05K 3/28 (2013.01); H05K 3/3436 (2013.01); H05K 3/3452 (2013.01); H01L 23/49822 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/15311 (2013.01); H05K 2201/10734 (2013.01); H05K 2203/058 (2013.01);
Abstract

A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.


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