The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2020
Filed:
Oct. 24, 2017
Mentor Graphics Corporation, Wilsonville, OR (US);
Suresh Krishnamurthy, Noida, IN;
Deepak Kumar Garg, Noida, IN;
Sudhanshu Jayaswal, Noida, IN;
Saurabh Khaitan, Noida, IN;
Sanjay Gupta, Noida, IN;
John R. Stickley, Lake Oswego, OR (US);
Russell Elias Vreeland, III, Seal Beach, CA (US);
Ronald James Squiers, Castro Valley, CA (US);
Abhijit Das, Delhi, IN;
Charles W. Selvidge, Oakland, CA (US);
Mentor Graphics Corporation, Wilsonville, OR (US);
Abstract
Aspects of the disclosed technology relate to techniques of latency test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates arrival time information with messages when the messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device, and associates latency information with the messages when the messages are dispatched by the hardware model of the circuit design. The arrival time information of a particular message and the latency information are determined with respect to a model time reference provided in the reconfigurable hardware modeling device.