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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10651315 B1

PDFFull Text
Date of Patent:
May. 12, 2020

Filed:

Dec. 17, 2012

Three dimensional memory

Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Zhenyu Lu, Boise, ID (US);

Hongbin Zhu, Boise, ID (US);

Gordon A Haller, Boise, ID (US);

Roger W. Lindsay, Boise, ID (US);

Andrew Bicksler, Boise, ID (US);

Brian J. Cleereman, Boise, ID (US);

Minsoo Lee, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:

Wells St. John P.S.

Primary Examiner:

Matthew L Reames

Assistant Examiner:

John A Bodnar

Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11524 (2017.01); H01L 21/225 (2006.01); H01L 27/11556 (2017.01); H01L 29/788 (2006.01); H01L 27/11568 (2017.01); H01L 27/11565 (2017.01); H01L 27/11519 (2017.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 27/1157 (2017.01); H01L 21/285 (2006.01); H01L 23/535 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 29/788 (2013.01); H01L 21/28518 (2013.01); H01L 23/535 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7889 (2013.01); H01L 29/792 (2013.01); H01L 29/7926 (2013.01);
Abstract

A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

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