The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Jul. 30, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tsung-Han Wu, Tainan, TW;

Tong-Min Weng, Taoyuan, TW;

Chun-Yi Huang, Hsinchu, TW;

Po-Ching Lee, Hsinchu, TW;

Chih-Hsuan Hsieh, Hsinchu, TW;

Shu-Ching Tsai, Pingtung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/324 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66803 (2013.01); H01L 21/02164 (2013.01); H01L 21/02236 (2013.01); H01L 21/26586 (2013.01); H01L 21/324 (2013.01); H01L 29/7851 (2013.01);
Abstract

Methods of fabricating FinFET devices are provided. The method includes forming a fin over a substrate. The method also includes implanting a first dopant on a top surface of the fin and implanting a second dopant on a sidewall surface of the fin. The first dopant is different from the second dopant. The method further includes forming an oxide layer on the top surface and the sidewall surface of the fin, and forming a gate electrode layer over the oxide layer.


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