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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10651202 B1

PDFFull Text
Date of Patent:
May. 12, 2020

Filed:

Nov. 20, 2018

3d circuit transistors with flipped gate

Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Francois Andrieu, Saint-Ismier, FR;

Perrine Batude, Dijon, FR;

Maud Vinet, Claix, FR;

Assignee:

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris, FR;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Fernando L Toledo

Assistant Examiner:

Neil R Prasad

Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/84 (2006.01); H01L 21/762 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 27/06 (2006.01); H01L 21/822 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 23/532 (2006.01); H01L 21/033 (2006.01); H01L 21/768 (2006.01); H01L 21/285 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/76251 (2013.01); H01L 21/8221 (2013.01); H01L 21/823437 (2013.01); H01L 21/84 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 27/0688 (2013.01); H01L 27/088 (2013.01); H01L 27/1207 (2013.01); H01L 27/1288 (2013.01); H01L 21/0337 (2013.01); H01L 21/28518 (2013.01); H01L 21/76275 (2013.01); H01L 21/76283 (2013.01); H01L 21/76805 (2013.01); H01L 21/76807 (2013.01); H01L 21/823475 (2013.01); H01L 21/823828 (2013.01); H01L 21/823871 (2013.01); H01L 23/53228 (2013.01); H01L 23/53257 (2013.01); H01L 27/092 (2013.01);
Abstract

An integrated circuit is provided with several superimposed levels of transistors, the circuit including an upper level provided with transistors having a rear gate electrode laid out on a first semiconducting layer, and a second semiconducting layer, a first transistor among the transistors of the upper level being provided with a contact pad traversing the second semiconducting layer, the contact pad being connected to a connection zone disposed between the first semiconducting layer and the second semiconducting layer, the first transistor being polarised by and connected to at least one power supply line disposed on a side of a front face of the second semiconducting layer that is opposite to the rear face.

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