The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Jan. 28, 2019
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Alban Zaka, Dresden, DE;

Luca Pirro, Dresden, DE;

Tom Herrmann, Dresden, DE;

El Mehdi Bazizi, Dresden, DE;

Jan Hoentschel, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7838 (2013.01); H01L 29/1033 (2013.01);
Abstract

One illustrative integrated circuit product disclosed herein includes at least one transistor formed on an active region of on an SOI substrate, the transistor comprising a gate that includes a gate structure, first and second source/drain regions positioned on opposite sides of the gate, the first and second source/drain regions comprising doped epitaxial semiconductor material that is doped with a dopant material of a first type, and a doped region positioned below the gate, wherein the doped region has a lateral width that is at least substantially equal to the CPP (contact-poly-pitch) dimension of the transistor and is doped with a dopant material of the first type, wherein a first portion of the doped region is positioned vertically above an interface between the active region and a buried insulation layer of the SOI substrate and a second portion of the doped region is positioned vertically below the interface.


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