The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Dec. 28, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Andrew Collins, Chandler, AZ (US);

Bharat P. Penmecha, Chandler, AZ (US);

Rajasekaran Swaminathan, Chandler, AZ (US);

Ram Viswanath, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/528 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 23/49838 (2013.01); H01L 23/5381 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 24/17 (2013.01); H01L 24/23 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01);
Abstract

Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.


Find Patent Forward Citations

Loading…