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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10636769 B1

PDFFull Text
Date of Patent:
Apr. 28, 2020

Filed:

Sep. 10, 2018

Semiconductor package having spacer layer

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Weng Hong Teh, Phoenix, AZ (US);

John S. Guzek, Chandler, AZ (US);

Shan Zhong, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Schwabe, Williamson & Wyatt, P.C.

Primary Examiner:

Feifei Yeung Lopez

Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/12 (2006.01); H01L 25/10 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/12 (2013.01); H01L 23/13 (2013.01); H01L 23/3128 (2013.01); H01L 23/498 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/49894 (2013.01); H01L 23/5389 (2013.01); H01L 25/105 (2013.01); H01L 23/3121 (2013.01); H01L 23/49816 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/14181 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/73 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06575 (2013.01); H01L 2924/1461 (2013.01);
Abstract

Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.

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