The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

Oct. 07, 2019
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Margaret A. Szymanowski, Chandler, AZ (US);

Sarmad K. Musa, Gilbert, AZ (US);

Fernando A. Santos, Chandler, AZ (US);

Mahesh K. Shah, Scottsdale, AZ (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/02 (2006.01); H03F 3/213 (2006.01); H01L 23/552 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 23/495 (2006.01); H01L 21/48 (2006.01); H03F 3/195 (2006.01); H01L 23/66 (2006.01); H01L 23/492 (2006.01); H01L 23/31 (2006.01); H03F 3/21 (2006.01);
U.S. Cl.
CPC ...
H03F 1/0288 (2013.01); H01L 21/4821 (2013.01); H01L 23/3121 (2013.01); H01L 23/492 (2013.01); H01L 23/49541 (2013.01); H01L 23/49575 (2013.01); H01L 23/552 (2013.01); H01L 23/66 (2013.01); H01L 24/49 (2013.01); H01L 24/85 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H03F 3/195 (2013.01); H03F 3/211 (2013.01); H03F 3/213 (2013.01); H01L 24/48 (2013.01); H01L 2223/6611 (2013.01); H01L 2223/6644 (2013.01); H01L 2224/45099 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48195 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/49175 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19105 (2013.01); H01L 2924/19107 (2013.01); H01L 2924/3011 (2013.01); H01L 2924/3025 (2013.01); H03F 2200/451 (2013.01); H03F 2203/21106 (2013.01);
Abstract

A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.


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