The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

Dec. 14, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Andrew M. Greene, Albany, NY (US);

John R. Sporre, Albany, NY (US);

Stan Tsai, Clifton Park, NY (US);

Ruilong Xie, Schenectady, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/3105 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/31055 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/0653 (2013.01); H01L 29/401 (2013.01); H01L 29/42376 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/31144 (2013.01);
Abstract

Embodiments are directed to methods of forming a semiconductor device and resulting structures for improving gate height control and providing interlayer dielectric (ILD) protection during replacement metal gate (RMG) processes. The method includes forming a semiconductor fin on a substrate. A sacrificial gate is formed over a channel region of the semiconductor fin, and an oxide hard mask is formed on a surface of the sacrificial gate. An interlayer dielectric (ILD) is formed adjacent to the sacrificial gate. The ILD is recessed below a surface of the oxide hard mask, and a nitride layer is formed on a surface of the recessed ILD.


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