The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2020
Filed:
Nov. 15, 2018
Intel Corporation, Santa Clara, CA (US);
Michael J. Bernhardt, Boise, ID (US);
Yudong Kim, Boise, ID (US);
Denzil S. Frost, Boise, ID (US);
Tuman Earl Allen, III, Kuna, ID (US);
Kevin Lee Baker, Los Gatos, CA (US);
Kolya Yastrebenetsky, Boise, ID (US);
Ronald Allen Weimer, Boise, ID (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.