The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2020

Filed:

Dec. 20, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Daqiao Du, Lake Oswego, OR (US);

Zhen Zhou, Chandler, AZ (US);

Jun Liao, Hillsboro, OR (US);

James A. McCall, Portland, OR (US);

Xiang Li, Portland, OR (US);

Kai Xiao, Portland, OR (US);

Zhichao Zhang, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 1/05 (2006.01); H05K 1/11 (2006.01); H05K 1/14 (2006.01); H01R 12/72 (2011.01); H05K 3/36 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0284 (2013.01); H05K 1/05 (2013.01); H05K 1/111 (2013.01); H05K 1/115 (2013.01); H05K 1/117 (2013.01); H05K 1/141 (2013.01); H01R 12/721 (2013.01); H05K 1/0218 (2013.01); H05K 1/0219 (2013.01); H05K 1/142 (2013.01); H05K 3/366 (2013.01); H05K 2201/0723 (2013.01); H05K 2201/0919 (2013.01); H05K 2201/09063 (2013.01); H05K 2201/09236 (2013.01); H05K 2201/10189 (2013.01);
Abstract

A system for a three-dimensional ('3D') printed circuit board ('PCB') to printed circuit board interface is provided. A first PCB includes first landing pads disposed on one or more edges of the first PCB. The first landing pads electrically couple to conductive pins or second landing pads disposed on a second PCB. The second landing pads may be disposed in a slot in the second PCB. The interface between the first landing pads and the second landing pads may provide various advantages over traditional PCB to PCB interfaces, such as, improved signal integrity, improved power integrity, increased contact density, decreased clock jitter, etc.


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