The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2020
Filed:
Jul. 03, 2017
Cadence Design Systems, Inc., San Jose, CA (US);
Zhuo Li, Austin, TX (US);
Wen-Hao Liu, Cedar Park, TX (US);
Gracieli Posser, Austin, TX (US);
Charles Jay Alpert, Cedar Park, TX (US);
Ruth Patricia Jackson, Cambridge, GB;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Various embodiments provide for routing a net of a circuit design using multiple layer ranges. In particular, some embodiments route a net of a circuit design using multiple layer ranges by performing routing of the net over multiple iterations such that at each iteration, a layer bound of a layer range is gradually adjusted (e.g., relaxed) based on wirelength, wire detour, or congestion of a routing result of a prior iteration. For instance, some embodiments may gradually relax a layer bound of the layer range by increasing a layer upper bound or decreasing a layer lower bound.