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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10566256 B1

PDFFull Text
Expired
Date of Patent:
Feb. 18, 2020

Filed:

Jan. 04, 2018

Testing method for testing wafer level chip scale packages

Applicant:

Winway Technology Co., Ltd., Kaohsiung, TW;

Inventors:

Kuan-Chung Chen, Kaohsiung, TW;

Cheng-Hui Lin, Kaohsiung, TW;

Chia-Pin Sun, Kaohsiung, TW;

Assignee:

WINWAY TECHNOLOGY CO., LTD., Kaohsiung, TW;

Attorney:

Muncy, Geissler, Olds & Lowe, PC

Primary Examiner:

Alvaro E Fortich

Int. Cl.
CPC ...
G01R 1/06 (2006.01); H01L 21/66 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); G01R 31/28 (2006.01); G01R 1/073 (2006.01); G01R 1/067 (2006.01);
U.S. Cl.
CPC ...
H01L 22/34 (2013.01); G01R 1/06733 (2013.01); G01R 1/073 (2013.01); G01R 1/07307 (2013.01); G01R 1/07314 (2013.01); G01R 31/2886 (2013.01); H01L 21/6836 (2013.01); H01L 24/06 (2013.01); G01R 1/06722 (2013.01); G01R 31/2831 (2013.01); H01L 24/13 (2013.01); H01L 2224/056 (2013.01); H01L 2224/0556 (2013.01); H01L 2924/00014 (2013.01);
Abstract

A testing method for testing wafer level chip scale packages formed on a wafer including a wafer substrate and spaced-apart contact electrodes disposed on the wafer substrate, includes: providing a test device including a probe card formed with a plurality of parallel probe holes having a uniform cross-sectional dimension, and a plurality of probes respectively received in the probe holes and extending respectively in the probe holes along axes of the probe holes; and electrically connecting the contact electrodes to the probes. A distance between the axes of two adjacent ones of the probe holes is equal to a smallest spacing between two adjacent ones of the contact electrodes and is not greater than 0.5 mm.

Find Patent Forward Citations

Chen, Kuan-Chung. (2020). Testing method for testing wafer level chip scale packages (U.S. Patent No. 10566256). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10566256

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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