The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2020
Filed:
Jul. 01, 2019
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Wei-Cheng Lin, Taichung, TW;
Chih-Liang Chen, Hsinchu, TW;
Chih-Ming Lai, Hsinchu, TW;
Charles Chew-Yuen Young, Cupertino, CA (US);
Jiann-Tyng Tzeng, Hsinchu, TW;
Kam-Tou Sio, Zhubei, TW;
Ru-Gun Liu, Zhubei, TW;
Shih-Wei Peng, Hsinchu, TW;
Wei-Chen Chien, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method of fabricating an integrated circuit is disclosed. The method includes defining a via grid, generating a first layout design of the integrated circuit based on at least the via grid or design criteria, generating a standard cell layout design of the integrated circuit, generating a via color layout design of the integrated circuit based on the first layout design and the standard cell layout design, performing a color check on the via color layout design based on design rules, and fabricating the integrated circuit based on at least the via color layout design. The first layout design has a first set of vias arranged in first rows and first columns based on the via grid. The standard cell layout design has standard cells and a second set of vias arranged in the standard cells. The via color layout design has a third set of vias.