The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 11, 2020
Filed:
Dec. 24, 2015
Intel Corporation, Santa Clara, CA (US);
Karthik Jambunathan, Hillsboro, OR (US);
Glenn A. Glass, Portland, OR (US);
Anand S. Murthy, Portland, OR (US);
Jacob M. Jensen, Beaverton, OR (US);
Daniel B. Aubertine, North Plains, OR (US);
Chandra S. Mohapatra, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Tensile strain is applied to a channel region of a transistor by depositing an amorphous SiGeCalloy in at least one of a source and a drain (S/D) region of the transistors. The amorphous SiGeCalloy is crystallized, thus reducing the unit volume of the alloy. This volume reduction in at least one of the source and the drain region applies strain to a connected channel region. This strain improves electron mobility in the channel. Dopant activation in the source and drain locations is recovered during conversion from amorphous to crystalline structure. Presence of high carbon concentrations reduces dopant diffusion from the source and drain locations into the channel region. The techniques may be employed with respect to both planar and non-planar (e.g., FinFET and nanowire) transistors.