The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Nov. 26, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Andrew M. Bayless, Boise, ID (US);

James M. Derderian, Boise, ID (US);

Xiao Li, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/304 (2006.01); H01L 21/306 (2006.01); H01L 23/28 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/29 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76834 (2013.01); H01L 21/02041 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/298 (2013.01); H01L 23/3128 (2013.01);
Abstract

A method for processing semiconductor dice comprises removing material from a surface of a semiconductor wafer to create a pocket surrounded by a sidewall at a lateral periphery of the semiconductor wafer, forming a film on a bottom of the pocket and securing semiconductor dice to the film in mutually spaced locations. A dielectric molding material is placed in the pocket over and between the semiconductor dice, material is removed from another surface of the semiconductor wafer to expose the film, bond pads of the semiconductor dice are exposed, redistribution layers in electrical communication with the bond pads of associated semiconductor dice are formed, and the redistribution layers and associated semiconductor dice are singulated along spaces between the semiconductor dice.


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