The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2020
Filed:
May. 15, 2017
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Jeng-Shyan Lin, Tainan, TW;
Dun-Nian Yaung, Taipei, TW;
Jen-Cheng Liu, Hsinchu, TW;
Wen-De Wang, Minsyong Township, TW;
Shuang-Ji Tsai, Tainan, TW;
Yueh-Chiou Lin, Taichung, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed.