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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10535670 B1

PDFFull Text
Date of Patent:
Jan. 14, 2020

Filed:

Feb. 25, 2016

Non-volatile memory having an erase gate formed between two floating gates with two word lines formed on other sides and a method for forming the same

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chien-Hsuan Liu, Tainan, TW;

Chiang-Ming Chuang, Changhua, TW;

Chih-Ming Lee, Tainan, TW;

Kun-Tsang Chuang, Miaoli County, TW;

Hung-Che Liao, Tainan, TW;

Chia-Ming Pan, Tainan, TW;

Hsin-Chi Chen, Tainan, TW;

Assignee:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Attorney:

JCIPRNET

Primary Examiner:

Anh D Mai

Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H01L 27/11521 (2017.01); H01L 21/28 (2006.01); H01L 27/11531 (2017.01); H01L 27/11541 (2017.01); H01L 21/3213 (2006.01); H01L 27/11519 (2017.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 21/32135 (2013.01); H01L 27/11519 (2013.01); H01L 27/11531 (2013.01); H01L 27/11541 (2013.01); H01L 29/40114 (2019.08); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01);
Abstract

A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.

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