The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2020

Filed:

Dec. 27, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chun-Han Tsao, New Taipei, TW;

Chii-Ming Wu, Taipei, TW;

Cheng-Yuan Tsai, Chu-Pei, TW;

Yi-Huan Chen, Hsin Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 27/092 (2006.01); H01L 21/8234 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823857 (2013.01); H01L 21/82345 (2013.01); H01L 21/823443 (2013.01); H01L 21/823835 (2013.01); H01L 21/823864 (2013.01); H01L 27/0922 (2013.01); H01L 29/4966 (2013.01); H01L 29/4975 (2013.01); H01L 29/66545 (2013.01); H01L 21/823462 (2013.01); H01L 21/823842 (2013.01); H01L 29/513 (2013.01);
Abstract

Some embodiments relate to an integrated circuit including a semiconductor substrate including a multi-voltage device region. A first pair of source/drain regions are spaced apart from one another by a first channel region. A dielectric layer is disposed over the first channel region. A barrier layer is disposed over the dielectric layer. A fully silicided gate is disposed over the first channel region and is vertically separated from the semiconductor substrate by a work function tuning layer. The work function tuning layer separates the fully silicided gate from the barrier layer.


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