The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2020
Filed:
Apr. 28, 2016
Applicant:
Globalfoundries Singapore Pte. Ltd., Singapore, SG;
Inventors:
Assignee:
GLOBALFOUNDRIES SINGAPORE PTE. LTD., Singapore, SG;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 27/12 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/84 (2006.01); H01L 21/3105 (2006.01); H01L 21/32 (2006.01); H01L 21/311 (2006.01); H01L 21/77 (2017.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/02238 (2013.01); H01L 21/02532 (2013.01); H01L 21/02653 (2013.01); H01L 21/31053 (2013.01); H01L 21/32 (2013.01); H01L 21/76283 (2013.01); H01L 21/84 (2013.01); H01L 27/127 (2013.01); H01L 27/1222 (2013.01); H01L 27/1233 (2013.01); H01L 27/1251 (2013.01); H01L 27/1262 (2013.01); H01L 27/1288 (2013.01); H01L 29/1054 (2013.01); H01L 29/66431 (2013.01); H01L 29/66575 (2013.01); H01L 29/66651 (2013.01); H01L 29/66659 (2013.01); H01L 29/778 (2013.01); H01L 21/02639 (2013.01); H01L 21/31144 (2013.01); H01L 29/665 (2013.01); H01L 29/6656 (2013.01); H01L 29/7824 (2013.01); H01L 2021/775 (2013.01);
Abstract
Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a substrate including a semiconductor layer over an insulator layer. The method includes selectively replacing portions of the semiconductor layer with insulator material to define an isolated semiconductor layer region. Further, the method includes selectively forming a relaxed layer on the isolated semiconductor layer region. Also, the method includes selectively forming a strained layer on the relaxed layer. The method forms a device over the strained layer.