IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10529671 B1

PDFFull Text
Date of Patent:
Jan. 07, 2020

Filed:

Jul. 03, 2017

Package structure and method for forming the same

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hsiao-Wen Lee, Hsinchu, TW;

Hsien-Wen Liu, Hsinchu, TW;

Shin-Puu Jeng, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

Birch, Stewart, Kolasch & Birch, LLP

Primary Examiner:

Ismail A Muse

Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 21/304 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01); H01L 21/02 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/0223 (2013.01); H01L 21/3043 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); H01L 23/3135 (2013.01); H01L 23/3178 (2013.01); H01L 23/3192 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 21/486 (2013.01); H01L 23/5384 (2013.01); H01L 2221/68327 (2013.01);
Abstract

Package structures and methods for forming the same are provided. A fan-out package structure includes a semiconductor substrate. The package structure also includes a connector over a top surface of the semiconductor substrate. The package structure further includes a buffer layer surrounding the connector and overlying a sidewall of the semiconductor substrate. In addition, the package structure includes an encapsulation layer surrounding the buffer layer. The buffer layer is between the encapsulation layer and the sidewall of the semiconductor substrate. The package structure also includes a redistribution layer (RDL) over the buffer layer and the encapsulation layer. The redistribution layer is electrically connected to the connector.

Find Patent Forward Citations

Loading…