The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Nov. 13, 2018
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Priyadarshi Panda, Newark, CA (US);

Gill Lee, San Jose, CA (US);

Srinivas Gandikota, Santa Clara, CA (US);

Sung-Kwan Kang, San Jose, CA (US);

Sanjay Natarajan, Portland, OR (US);

Assignee:

APPLIED MATERIALS, INC., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67184 (2013.01); H01L 21/67155 (2013.01); H01L 21/67161 (2013.01);
Abstract

Methods and apparatuses for substrate fabrication are provided herein. The apparatus, for example, can include a cluster tool including a vacuum transfer module (VTM) configured to receive, under vacuum conditions, a silicon substrate with a polysilicon plug (poly plug) and transfer, without vacuum break, the substrate to and from a plurality of processing chambers each independently connected to the VTM for performing a corresponding one of a plurality of DRAM bit line processes on the substrate, the plurality of processing chambers comprising a pre-cleaning chamber configured to remove native oxide from a surface of the substrate, a barrier metal deposition chamber configured to deposit the barrier metal on the surface of the poly plug on the silicon substrate, a barrier layer deposition chamber configured to deposit at least one material on the surface of the barrier metal, a bit line metal deposition chamber configured to deposit at least one material on the surface of the barrier layer, and a hard mask deposition chamber configured to deposit at least one material on the surface of the bit line metal.


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