The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Apr. 05, 2017
Applicant:

Crossbar, Inc., Santa Clara, CA (US);

Inventors:

Sundar Narayanan, Cupertino, CA (US);

Zhen Gu, Cupertino, CA (US);

Natividad Vasquez, San Francisco, CA (US);

Assignee:

Crossbar, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/1608 (2013.01);
Abstract

Two-terminal memory devices can be formed in part within a dielectric material that is electrically insulating and operates as a blocking layer to mitigate diffusion of metal particles employed in integrated circuit fabrication. This dielectric material can be protected from other fabrication processes corrosive to the dielectric material (e.g., CMP, HF clean, etc) by a silicon containing liner. Use of the silicon containing liner can enable a minimum thickness of the dielectric material to be preserved and can facilitate step height differences between adjacent material surfaces that form a two-terminal memory device to be on the order of less than about five angstroms. This small step height difference, particularly when underlying a switching layer of the two-terminal memory device, can yield excellent switching characteristics.


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