The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2019

Filed:

Jul. 24, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Sin-Yao Huang, Tainan, TW;

Ching-Chun Wang, Tainan, TW;

Dun-Nian Yaung, Taipei, TW;

Feng-Chi Hung, Chu-Bei, TW;

Ming-Tsong Wang, Taipei, TW;

Shih Pei Chou, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1464 (2013.01); H01L 27/1469 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01);
Abstract

Some embodiments relate to a method. In the method, a CMOS substrate, which includes a plurality of CMOS devices, is received. An interconnect structure including a plurality of metal layers is formed over the CMOS substrate, wherein a first metal layer of the metal layers is nearest the CMOS substrate and an Nth of the metal layers is furthest from the CMOS substrate. An image sensor substrate is bonded to the interconnect structure. A first mask is formed over the image sensor substrate, and a first etch is performed with the first mask in place to expose an upper surface of the first metal layer. A conductive bond pad material is formed in direct contact with the exposed first metal layer.


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