The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2019
Filed:
Nov. 21, 2017
Lam Research Corporation, Fremont, CA (US);
Xiang Zhou, Santa Clara, CA (US);
Ganesh Upadhyaya, Pleasanton, CA (US);
Yoshie Kimura, Castro Valley, CA (US);
Weiye Zhu, Fremont, CA (US);
Zhaohong Han, Union City, CA (US);
Seokhwan Lee, San Jose, CA (US);
Noel Sun, Sunnyvale, CA (US);
Lam Research Corporation, Fremont, CA (US);
Abstract
Methods and apparatuses for passivating a fin field effect transistor (FinFET) semiconductor device and performing a gate etch using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include performing a partial gate etch, depositing a passivation layer on exposed surfaces of semiconductor fins and a gate layer by ALD, and performing a final gate etch to form one or more gate structures of the FinFET semiconductor device. The etch, deposition, and etch processes are performed in the same plasma chamber. The passivation layer is deposited on sidewalls of the gate layer to maintain a gate profile of the one or more gate structures during etching.