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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10510763 B1

PDFFull Text
Date of Patent:
Dec. 17, 2019

Filed:

May. 26, 2017

Embedded nonvolatile memory and forming method thereof

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chang-Ming Wu, New Taipei, TW;

Wei-Cheng Wu, Hsinchu County, TW;

Yuan-Tai Tseng, Hsinchu County, TW;

Shih-Chang Liu, Kaohsiung, TW;

Chia-Shiung Tsai, Hsinchu, TW;

Ru-Liang Lee, Hsinchu, TW;

Harry Hak-Lay Chuang, Singapore, SG;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

Maschoff Brennan

Primary Examiner:

Chandra Chaudhari

Int. Cl.
CPC ...
H01L 27/11521 (2017.01); H01L 21/28 (2006.01); H01L 21/3213 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/3205 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/31111 (2013.01); H01L 21/32055 (2013.01); H01L 21/32133 (2013.01); H01L 21/32137 (2013.01); H01L 21/768 (2013.01); H01L 23/528 (2013.01); H01L 23/5329 (2013.01); H01L 23/53271 (2013.01); H01L 29/40114 (2019.08); H01L 29/4238 (2013.01); H01L 29/42328 (2013.01); H01L 29/4916 (2013.01); H01L 29/6656 (2013.01); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

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