The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 17, 2019
Filed:
Jul. 19, 2016
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Kam-Tou Sio, Zhubei, TW;
Chih-Ming Lai, Hsinchu, TW;
Chun-Kuang Chen, Guanxi Township, TW;
Chih-Liang Chen, Hsinchu, TW;
Charles Chew-Yuen Young, Cupertino, CA (US);
Chi-Yeh Yu, Hsinchu, TW;
Jiann-Tyng Tzeng, Hsin Chu, TW;
Ru-Gun Liu, Zhubei, TW;
Wen-Hao Chen, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
The present disclosure relates to an integrated circuit having a via rail that prevents reliability concerns such as electro-migration. In some embodiments, the integrated circuit has a first plurality of conductive contacts arranged over a semiconductor substrate. A first metal interconnect wire is arranged over the first plurality of conductive contacts, and a second metal interconnect wire is arranged over the first metal interconnect wire. A via rail is arranged over the first metal interconnect wire and electrically couples the first metal interconnect wire and the second metal interconnect wire. The via rail has a length that continuously extends over two or more of the plurality of conductive contacts. The length of via rail provides for an increased cross-sectional area both between the first metal interconnect wire and the second metal interconnect wire and along a length of the via rail, thereby mitigating electro-migration within the integrated circuit.