The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2019

Filed:

Apr. 09, 2018
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

Shruti Vivek Thombare, Sunnyvale, CA (US);

Raashina Humayun, Los Altos, CA (US);

Michal Danek, Cupertino, CA (US);

Chiukin Steven Lai, Sunnyvale, CA (US);

Joshua Collins, Sunnyvale, CA (US);

Hanna Bamnolker, Cupertino, CA (US);

Griffin John Kennedy, Berkeley, CA (US);

Gorun Butail, Fremont, CA (US);

Patrick A. van Cleemput, San Jose, CA (US);

Assignee:

Lam Research Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/768 (2006.01); H01L 21/285 (2006.01); H01L 23/522 (2006.01); H01L 27/11582 (2017.01); H01L 23/532 (2006.01); H01L 27/108 (2006.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
H01L 21/76864 (2013.01); H01L 21/28562 (2013.01); H01L 21/28568 (2013.01); H01L 21/76843 (2013.01); H01L 21/76876 (2013.01); H01L 21/76877 (2013.01); H01L 21/76879 (2013.01); H01L 23/5226 (2013.01); H01L 23/53266 (2013.01); H01L 27/10891 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01);
Abstract

Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.


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