The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2019
Filed:
Dec. 07, 2018
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Yu-Sheng Wang, Tainan, TW;
Chi-Cheng Hung, Tainan, TW;
Ching-Hwanq Su, Tainan, TW;
Liang-Yueh Ou Yang, New Taipei, TW;
Ming-Hsing Tsai, Chu-Pei, TW;
Yu-Ting Lin, Tainan, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/288 (2006.01); H01L 29/66 (2006.01); H01L 23/532 (2006.01); H01L 23/485 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76846 (2013.01); H01L 21/2885 (2013.01); H01L 21/76802 (2013.01); H01L 21/76862 (2013.01); H01L 21/76864 (2013.01); H01L 21/76873 (2013.01); H01L 23/485 (2013.01); H01L 23/53266 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01);
Abstract
A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.