The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2019
Filed:
Aug. 09, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Steven Hsu, Lake Oswego, OR (US);
Amit Agarwal, Hillsboro, OR (US);
Simeon Realov, Portland, OR (US);
Iqbal Rajwani, Roseville, CA (US);
Ram K. Krishnamurthy, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0016 (2013.01); G06F 17/5045 (2013.01);
Abstract
An apparatus is provided which comprises: a first inverter to receive a clock; a pass-gate coupled to the first inverter; a second inverter coupled to the pass-gate and to provide an output clock; and a device coupled to the second inverter and the pass-gate, wherein the transistor and the pass-gate are controllable by a logic that depends on logic values of at least two signals (e.g., an enable and the clock).