The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2019
Filed:
Mar. 07, 2018
United Microelectronics Corp., Hsin-Chu, TW;
Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;
Li-Wei Feng, Kaohsiung, TW;
Ying-Chiao Wang, Changhua County, TW;
Chien-Ting Ho, Taichung, TW;
Kai-Ping Chen, Tainan, TW;
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;
Abstract
A semiconductor structure having a contact plug includes a substrate. A memory cell region and a peripheral circuit region are defined on the substrate. At least one memory cell is disposed on the substrate within the memory cell region. The memory cell includes a transistor and a capacitor structure. A first planar stacked dielectric layer covers the peripheral circuit region. The first planar stacked dielectric layer includes two first dielectric layers and a second dielectric layer. The first dielectric layer at the bottom of the first planar stacked dielectric layer extends to the memory cell region and covers the capacitor structure. A contact plug is disposed at the peripheral circuit region and penetrates the first planar stacked dielectric layer.