The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

Aug. 25, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shao-Ming Koh, Hsinchu, TW;

Chen-Ming Lee, Taoyuan County, TW;

I-Wen Wu, Hsinchu, TW;

Fu-Kai Yang, Hsinchu, TW;

Jia-Heng Wang, Hsinchu, TW;

Mei-Yun Wang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/324 (2006.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/167 (2006.01); H01L 29/45 (2006.01); H01L 29/78 (2006.01); H01L 27/06 (2006.01); H01L 21/306 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823871 (2013.01); H01L 21/02063 (2013.01); H01L 21/324 (2013.01); H01L 21/76805 (2013.01); H01L 21/76814 (2013.01); H01L 21/76831 (2013.01); H01L 21/76889 (2013.01); H01L 21/76895 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 23/535 (2013.01); H01L 27/0605 (2013.01); H01L 27/0924 (2013.01); H01L 29/0847 (2013.01); H01L 29/16 (2013.01); H01L 29/161 (2013.01); H01L 29/167 (2013.01); H01L 29/1608 (2013.01); H01L 29/45 (2013.01); H01L 29/7845 (2013.01); H01L 21/3065 (2013.01); H01L 21/30604 (2013.01); H01L 21/823807 (2013.01);
Abstract

A method includes providing a structure that includes a substrate; first and second gate structures over the substrate; first and second source/drain (S/D) features over the substrate; a first dielectric layer over sidewalls of the first and second gate structures and the first and second S/D features; and a second dielectric layer over the first dielectric layer. The first and second S/D features are adjacent to the first and second gate structures respectively. The first and second S/D features comprise different materials. The method further includes etching the first and second dielectric layers to expose the first and second S/D features; doping a p-type dopant to the first and second S/D features; and performing a selective etching process to the first and second S/D features after the doping of the p-type dopant. The selective etching process recesses the first S/D feature faster than it recesses the second S/D feature.


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