The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

Apr. 19, 2018
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Wanbing Yi, Singapore, SG;

Curtis Chun-I Hsieh, Singapore, SG;

Yi Jiang, Singapore, SG;

Bharat Bhushan, Singapore, SG;

Mahesh Bhatkar, Singapore, SG;

Juan Boon Tan, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/22 (2006.01); H01L 43/12 (2006.01); H01L 23/522 (2006.01); H01L 43/02 (2006.01); H01L 43/08 (2006.01);
U.S. Cl.
CPC ...
H01L 43/12 (2013.01); H01L 23/5226 (2013.01); H01L 27/222 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01);
Abstract

Method of forming embedded MRAM in interconnects using a metal hard mask process and the resulting device are provided. Embodiments include forming a first interlayer dielectric (ILD) layer including a first metal (Mx) level; forming a capping layer over the first ILD layer; forming magnetic tunnel junction (MTJ) structures formed in a second ILD over the first capping layer; forming a second metal (Mx+1) level in the second ILD layer; forming a second capping layer over the second ILD layer; and forming a third metal (Mx+2) level in a third ILD layer over the second capping layer.


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