The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

Jun. 05, 2018
Applicant:

Phoenix Pioneer Technology Co., Ltd., Hsinchu County, TW;

Inventors:

Pao-Hung Chou, Hsinchu County, TW;

Shih-Ping Hsu, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 1/11 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/683 (2006.01); H01L 23/13 (2006.01); H05K 3/40 (2006.01); H05K 3/06 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); H01L 21/4857 (2013.01); H01L 21/6835 (2013.01); H01L 23/13 (2013.01); H05K 1/0296 (2013.01); H05K 1/111 (2013.01); H01L 21/486 (2013.01); H01L 23/49827 (2013.01); H01L 2221/68345 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H05K 1/0284 (2013.01); H05K 1/0298 (2013.01); H05K 3/061 (2013.01); H05K 3/40 (2013.01); H05K 2201/10378 (2013.01);
Abstract

The invention provides an interposer substrate and a method of fabricating the same. The method includes: etching a carrier to form a recessed groove thereon; filling a dielectric material in the recessed groove to form a first dielectric material layer, or forming a patterned first dielectric material layer on the carrier; forming a first wiring layer, a first conductive block and a second dielectric material layer on the carrier and the first dielectric material layer sequentially, with the first wiring layer and the first conductive block embedded in the second dielectric material layer; and forming a second wiring layer and a second conductive block on the second dielectric material layer. A coreless interposer substrate having fine pitches is thus fabricated.


Find Patent Forward Citations

Loading…