The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

Jun. 25, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tzuan-Horng Liu, Taoyuan, TW;

Chao-Hsiang Yang, Hsinchu, TW;

Hsien-Wei Chen, Hsinchu, TW;

Ming-Fa Chen, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 22/32 (2013.01); H01L 23/3157 (2013.01); H01L 23/49822 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/13 (2013.01); H01L 2224/0217 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05556 (2013.01); H01L 2224/06515 (2013.01); H01L 2224/13007 (2013.01);
Abstract

A package structure includes a semiconductor substrate, conductive pads, and conductive vias. The conductive pads are located on and electrically connected to the semiconductor substrate, and each have a testing region and a contact region comprising a core contact region and a buffer contact region, wherein along one direction, the conductive pads each have a maximum length less than a sum of a maximum length of the testing region and a maximum length of the buffer contact region. The conductive vias are respectively located on the core contact regions of the conductive pads.


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