Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers

Abstract

A method for correcting bit defects in a memory array is disclosed. The method comprises determining a margin area associated with a resistance distribution for the memory array, wherein the resistance distribution comprises a distribution of bit-cell resistances for all bits comprising the memory array, wherein the margin area is a bandwidth of bit-cell resistances centered around a reference point associated with a sense amplifier, wherein the bit-cell resistances of memory bit-cells associated with the margin area are ambiguous. The method further comprises forcing the bit-cell resistances of memory bit-cells associated with the margin area to short circuits. Finally, the method comprises replacing each short-circuited memory bit-cell with a corresponding redundant bit in the codeword associated with the short-circuited memory bit-cell.