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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10475895 B1

PDFFull Text
Date of Patent:
Nov. 12, 2019

Filed:

Jun. 21, 2017

Semiconductor device and method for manufacturing the same

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hsin-Che Chiang, Taipei, TW;

Ju-Yuan Tzeng, New Taipei, TW;

Chun-Sheng Liang, Changhua County, TW;

Shu-Hui Wang, Hsinchu, TW;

Chih-Yang Yeh, Hsinchu County, TW;

Jeng-ya David Yeh, New Taipei, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

McClure, Qualey & Rodack, LLP

Primary Examiner:

Mary A Wilczewski

Assistant Examiner:

Tsz K Chiu

Int. Cl.
CPC ...
H01L 21/82 (2006.01); H01L 21/8234 (2006.01); H01L 21/768 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 21/3213 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42364 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823462 (2013.01); H01L 27/0886 (2013.01); H01L 29/4966 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 21/3213 (2013.01); H01L 21/823821 (2013.01); H01L 21/823864 (2013.01); H01L 27/088 (2013.01); H01L 29/6681 (2013.01);
Abstract

A semiconductor device includes a substrate, a first dielectric layer, a first device and a second device. The first dielectric layer is disposed on the substrate. The first device is disposed on the first dielectric layer on a first region of the substrate, and includes two first spacers, a second dielectric layer and a first gate structure. The first spacers are separated to form a first trench. The second dielectric layer is disposed on side surfaces and a bottom surface of the first trench. The first gate structure is disposed on the second dielectric layer. The second device is disposed on a second region of the substrate, and includes two second spacers and a second gate structure. The second spacers are disposed on the first dielectric layer and are separated to form a second trench. The second gate structure is disposed on the substrate within the second trench.

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