The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2019

Filed:

Feb. 09, 2018
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Chih-Mou Lin, Tainan, TW;

Chin-Chia Kuo, Tainan, TW;

Ming-Hua Tsai, New Taipei, TW;

Su-Hua Tsai, Hsinchu, TW;

Pai-Tsang Liu, Hsinchu, TW;

Chiao-Yu Li, Tainan, TW;

Chun-Ning Wu, Tainan, TW;

Wei-Hsuan Chang, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 29/06 (2006.01); H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/3115 (2006.01); H01L 21/3215 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4983 (2013.01); H01L 21/28185 (2013.01); H01L 21/31155 (2013.01); H01L 29/0619 (2013.01); H01L 29/0653 (2013.01); H01L 29/512 (2013.01); H01L 29/66568 (2013.01); H01L 29/7841 (2013.01); H01L 21/28035 (2013.01); H01L 21/28079 (2013.01); H01L 21/32155 (2013.01);
Abstract

A high-voltage device includes a semiconductor substrate, a source diffusion region, a drain diffusion region, a channel diffusion region and a gate electrode. The source diffusion region and the drain diffusion region with a first conductive type are disposed in the semiconductor substrate. The channel diffusion region is disposed in the semiconductor substrate and between the source diffusion region and the drain diffusion region. The gate dielectric layer is disposed on the channel diffusion region and having a first modified portion with a second conductive type extending inwards from a first edge of the gate dielectric layer. The gate electrode is disposed on the gate electric layer, wherein the first modified portion, the gate electrode and the channel diffusion region at least partially overlap with each other.


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