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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10457548 B1

PDFFull Text
Date of Patent:
Oct. 29, 2019

Filed:

Jun. 22, 2015

Integrating mems structures with interconnects and vias

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kevin Lai Lin, Beaverton, OR (US);

Chytra Pawashe, Beaverton, OR (US);

Raseong Kim, Hillsboro, OR (US);

Ian A. Young, Portland, OR (US);

Kanwal Jit Singh, Portland, OR (US);

Robert L. Bristol, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Schwabe, Williamson & Wyatt, P.C.

Primary Examiner:

Selim U Ahmed

Int. Cl.
CPC ...
B81B 7/00 (2006.01); B81C 1/00 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
B81B 7/007 (2013.01); B81C 1/00246 (2013.01); B81C 1/00301 (2013.01); H01L 21/7682 (2013.01); H01L 21/76829 (2013.01); B81B 2203/0109 (2013.01); B81B 2203/0118 (2013.01); B81B 2207/015 (2013.01); B81B 2207/07 (2013.01); B81B 2207/092 (2013.01); B81B 2207/094 (2013.01); B81B 2207/095 (2013.01); B81C 2201/014 (2013.01); B81C 2201/0109 (2013.01); B81C 2203/0714 (2013.01); B81C 2203/0742 (2013.01); B81C 2203/0771 (2013.01); H01L 21/76807 (2013.01);
Abstract

A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.

Find Patent Forward Citations

Lin, Kevin. (2019). Integrating mems structures with interconnects and vias (U.S. Patent No. 10457548). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10457548

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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