The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

Apr. 07, 2017
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kuo-Cheng Ching, Zhubei, TW;

Zhi-Chang Lin, Zhubei, TW;

Guan-Lin Chen, Baoshan Township, TW;

Ting-Hung Hsu, MiaoLi, TW;

Jiun-Jia Huang, Beigang Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 21/02356 (2013.01); H01L 21/82385 (2013.01); H01L 21/823821 (2013.01); H01L 21/823864 (2013.01); H01L 27/0922 (2013.01); H01L 29/0649 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7842 (2013.01); H01L 29/7843 (2013.01); H01L 29/7848 (2013.01);
Abstract

A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.


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