The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Jan. 31, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Shih Wei Bih, Taichung, TW;

Han-Wen Liao, Taichung, TW;

Xuan-You Yan, Taichung, TW;

Yen-Yu Chen, Taichung, TW;

Chun-Chih Lin, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/3213 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/28114 (2013.01); H01L 21/32135 (2013.01); H01L 21/32137 (2013.01); H01L 27/092 (2013.01); H01L 29/42376 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 21/823828 (2013.01); H01L 21/823842 (2013.01); H01L 29/4966 (2013.01);
Abstract

A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.


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