The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2019
Filed:
Mar. 06, 2017
Applicant:
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
Inventors:
Li Chuan Tsai, Kaohsiung, TW;
Chih-Cheng Lee, Kaohsiung, TW;
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung, TW;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 24/17 (2013.01); H01L 21/4846 (2013.01); H01L 23/49811 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 2224/02333 (2013.01); H01L 2224/02335 (2013.01); H01L 2224/04 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/014 (2013.01);
Abstract
A semiconductor substrate includes a first dielectric layer, a first patterned conductive layer disposed in the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a first bump pad disposed in the second dielectric layer. The first bump pad is electrically connected to the first patterned conductive layer, and the first bump pad has a curved surface surrounded by the second dielectric layer.