The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Oct. 04, 2017
Applicant:

Mentor Graphics Corporation, Wilsonville, OR (US);

Inventors:

John L. Sturtevant, Portland, OR (US);

Shumay Dou Shang, Saratoga, CA (US);

Konstantinos G. Adam, Belmont, CA (US);

Assignee:

Mentor Graphics Corporation, Wilsonville, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G03F 1/00 (2012.01); G03F 7/00 (2006.01); G03F 7/20 (2006.01); G03F 1/84 (2012.01); G03F 1/72 (2012.01); G03F 1/70 (2012.01); G03F 1/36 (2012.01);
U.S. Cl.
CPC ...
G06F 17/5068 (2013.01); G03F 1/70 (2013.01); G03F 1/72 (2013.01); G03F 1/84 (2013.01); G03F 7/7065 (2013.01); G03F 7/70616 (2013.01); G06F 17/5009 (2013.01); G06F 17/5081 (2013.01); G03F 1/36 (2013.01);
Abstract

Aspects of the disclosed technology relate to techniques for using hotspot simulation to make wafer rework decisions. Metrology data of photoresist patterns created based on a layout design for a circuit design by a photolithographic processing step are received during a lithographic process. Hotspots of interest are selected based on comparing the metrology data with simulated metrology data associated with hotspots. The simulated metrology data and information of the hotspots are generated by performing lithographic simulation on the layout design before the lithographic process and stored in a library of potential hotspots. Lithography simulation is performed on the selected hotspots of interest using process conditions of the photolithographic processing step to generate simulated hotspot data. The simulated hotspot data are analyzed to determine whether rework of the one or more wafers or a wafer lot to which the one or more wafers belong is needed.


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