The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Jun. 30, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Omkar Karhade, Chandler, AZ (US);

Christopher L. Rumer, Chandler, AZ (US);

Nitin Deshpande, Chandler, AZ (US);

Robert M. Nickerson, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 21/54 (2006.01); H01L 23/04 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/54 (2013.01); H01L 21/565 (2013.01); H01L 23/04 (2013.01); H01L 23/3157 (2013.01); H01L 24/97 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06582 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15331 (2013.01); H01L 2924/181 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/18161 (2013.01);
Abstract

Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.


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