The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2019
Filed:
Oct. 15, 2017
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Shih-Hsien Chen, Kaohsiung, TW;
Meng-Jun Wang, Taichung, TW;
Ting-Chun Wang, New Taipei, TW;
Chih-Sheng Chang, Tainan, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53295 (2013.01); H01L 21/02115 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/7682 (2013.01); H01L 21/7685 (2013.01); H01L 21/76828 (2013.01); H01L 21/76832 (2013.01); H01L 21/76895 (2013.01); H01L 23/528 (2013.01); H01L 23/5222 (2013.01); H01L 23/53228 (2013.01);
Abstract
A method for fabricating semiconductor device includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a first metal interconnection and a second metal interconnection in the first IMD layer; removing part of the first IMD layer to form a recess between the first metal interconnection and the second metal interconnection; performing a curing process; and forming a second IMD layer on the first metal interconnection and the second metal interconnection.